LcdClockEnglish

project overview
Year	2020
Number of pixels	29
Grayscales / Colors	2
Illuminant	LCD
Power input	4.5 V, 100 µA
Contact person	Arne Rossius
Project website

The CMOS LCD Clock is a simple 24-hour clock made from 4000-series CMOS logic integrated circuits. The circuit was designed to require as few ICs as possible without making the clock hard to use. It displays the time (hours and minutes) on a large 7-segment liquid crystal display, provides two buttons to set the clock, and runs on battery power (3x AAA). A standard watch crystal is used as a timebase.

Hardware

Rev. 1.0

• Schematic (PNG)
• Schematic (EAGLE 4.x)
• PCB Layout (EAGLE 4.x)
• Construction kit instructions Rev. 1.0

Functional Description

The clock consists of 5 functional units:

• Quartz Oscillator
• Pre-Divider
• Minute and Hour Counters
• Set Buttons
• Display Drivers and LCD

Quartz Oscillator

The quartz oscillator is using a 4060 which provides most of the oscillator circuitry and a 14-stage binary divider. With a standard 32768 Hz watch crystal, this results in an output frequency of 2 Hz. Outputs from some of the other stages of the divider are available and are used for the LCD (see below). The frequency of the oscillator can be fine-tuned by adjusting the load capacitance on the crystal. To make the clock as accurate as possible, a trimmer capacitor is used to allow easy adjustment of the load capacitance, requiring only a screwdriver. It is important that the metal part of the trimmer which touches the screwdriver is connected to ground, otherwise a metal screwdriver will change the load capacitance and the final oscillator frequency can only be read after the screwdriver is removed again.

Pre-Divider

The pre-divider receives the 2 Hz signal from the 4060 and divides it down to 1/60 Hz, i.e. one pulse per minute. For this, the rather unusual 40102 IC is used. It contains a pre-settable 2-digit BCD down-counter. The actual count isn't available, but the CO/ZO (carry out/zero out) pin goes low when the count is zero. As the counter is using BCD (binary coded decimal), the maximum preset value is usually 99, so a division by 120 (from 2 Hz to 1/60 Hz) seems impossible. However, loading a digit with a value higher than 9 appears to work fine, so loading the counter with the binary value 0xB9 results in a counter value of 119. After loading, 119 clock pulses are needed until the counter reaches zero. The ZO signal is fed back to the SPE input (synchronous programming enable), so at the next (120th) clock pulse, rather than rolling over to 99, the counter is loaded with the externally set value of 119 instead. This means the CO output is low for 0.5 s (one 2 Hz period) every minute, and can thus be used as an input to the minute counter.

The pre-divider is also loaded immediately when the APE (asynchronous programming enable) input is asserted (and any clock pulses are ignored while APE remains asserted). This is useful so the clock can be set second-accurate.

Minute and Hour Counters

Each counter uses a 4518 dual BCD counter IC. Each IC consists of two independent BCD counters, which each count from 0 to 9 before overflowing back to 0. The schematic shows these two counters as individual units, although they're located on the same microchip. The counting sequence is fine for the units digit, but the minute tens digit has to go from 5 to 0, and the hours have to jump back to 00 after 23, so extra circuitry is needed. The counters have reset inputs to set them back to 0, so all that's needed is an AND gate. The 4081 IC provides 4 independent AND gates. For the minute counter, the tens counter is reset when its 2¹ ("B") and 2² ("C") outputs are both high at the same time (which happens when the count is 6), and both hour counters are reset when the units counter's 2² ("C") and the tens counter's 2¹ ("B") outputs are both high at the same time (i.e. the count has reached 24).

The counters also come with a convenient OR gate connected to the clock input, with one true and one inverted input. This is useful to connect the set buttons, which would otherwise require an additional IC to combine their signals with the output of the previous stage (the pre-divider for the minutes clock, and the minute output for the hour clock). The set buttons can only work if the other input of the OR gate isn't asserted (high for the non-inverted, low for the inverted input), otherwise the OR gate's output is constantly high and no clock signal will be generated when pushing the button. Likewise, the buttons must leave their inputs on the OR gate in the non-asserted state when not pushed so the pulses from the previous stage can get through.

As the output from the pre-divider is only low for half a second every minute, it is connected to the inverted input of the counter. It will lock out the minute set button during this half second, but it is rather unlikely that the button is pressed during this time, and even if it is, pressing it again half a second later will work again. For the hour counter, the reset signal for the minute counter is used, which is only high for as long as it takes for the counter to rest itself, i.e. a very short time (a few microseconds). As the signal is low the rest of the time, it is connected to the non-inverting input of the hour counter.

The tens counters are clocked from the 2³ ("D") output of the corresponding units counters, which becomes high when the units count changes from 7 to 8, and low again when the count changes from 9 to 0. As the tens counter should increment when the units counter changes from 9 to 0, the inverted input is used so the count advances on the falling edge (high to low transition). As the other input of the tens counters is unused, there is no issue with the signal remaining asserted the whole time until the units counter reaches 8 again.

Set Buttons

The set buttons advance their corresponding counters by one every time they're pressed. Mechanical buttons have "bounce", which means when it is pressed, the electrical connection closes and opens several times for a few milliseconds before the contact is permanently closed, and the same can happen when the button is released. If the button were connected to the clock input of a counter directly, every bounce would increment the counter, making button operation very erratic. To avoid this, a debouncing circuit is needed betweeen the button and the clock input. This design uses a capacitor that is rapidly discharged when the button is pressed (through the 270 Ω resistor) and slowly charged again after the button is released (through the 100 kΩ resistor). The time between bounces is too short for the capacitor to charge again, so the output doesn't change. The capacitor and charge resistor are chosen so the capacitor can't charge to a significant voltage during bounces, but charges enough between two presses of the button. With a quick finger, the time between button release and the next button press can be as low as 20 ms. The 270 Ω resistor is needed to protect the button: without it, the capacitor discharge current would only be limited by the internal resistance of the capacitor and button and the circuit board traces, exceeding the specified current for the button and severely reducing its lifetime.

The signal on the capacitor rises slowly as the capacitor is charging, but the clock input expects a quick transition between the two logic states (low, i.e. close to ground level, and high, i.e. close to the supply voltage). For this reason, resistors are connected across the two remaining AND gates, thereby creating a hysteresis. If the AND gate's output is high, it also pulls the input high through a feedback resistor, so the voltage on the input resistor must be close to ground level before the gate's input will detect a low level. Once it does detect a low level, the output starts changing to low and thereby pulls the input even lower through the feedback resistor, making the output change state even faster. This is called a Schmitt-trigger circuit. Some ICs provide logic gates with Schmitt-trigger inputs, but no AND gates with Schmitt-trigger inputs are available in the 4000 family (only NAND gates).

Display Drivers and LCD

A liquid crystal display consists of two glass plates with a liquid between them. The glass plates have transparent metal electrodes in the shape of the segments on them. If an AC waveform is applied between two electrodes, the crystals in the liquid rotates, also rotating the polarisation of any light passing through that area. Polarisation filters in front of and behind the LCD determine if the non-rotated or the rotated light can pass -- for the LCD used in the clock, the non-rotated polarisation can pass, causing the background of the LCD to appear bright and the active segments to appear dark. The display for the clock is the simplest type of LCD, called a "static" LCD. This means that one of the glass plates is completely covered with a single electrode, which is called the backplane (BP). This means there is no "multiplexing" and every segment has its own electrode (and its own pin) on the other glass plate.

It is very important that LCDs are driven with an AC waveform with no "DC component" (that means the average, over time, of the voltage between the backplane and a segment is zero) to avoid degrading. The simplest way to generate an AC waveform is to connect a square wave with 50% duty cycle (i.e. a signal that changes between high and low with a constant frequency, and the high period is exactly as long as the low period) to the backplane, and then applying the inverted signal to segments that should be visible. This causes the voltage between the electrodes to change between the supply voltage Vdd (+4.5V with fresh batteries) and the negative supply voltage −Vdd, and the average is zero (50% * +Vdd + 50% * −Vdd = 0).

Fortunately, suitable square wave signals with different frequencies are available from the various stage outputs on the 4060 IC. The frequency for the LCD should be high enough to avoid flicker (at least 30 Hz), but not too high as every time the polarity across the LCD changes, a little bit of power is consumed (the electrodes on the two glass plates form a capacitor). For the clock, output Q9 was chosen, which provides 32768 Hz / 2⁹ = 64  Hz. To make the colon show up, an inverted signal would be required, but none is available without the use of an additional inverter IC. Instead, the 128 Hz output of the 4060 is connected to the colon. This signal changes its state twice as often as the backplane signal, resulting in the voltage over the colon going through 4 states during each 64 Hz cycle:

• 00 (both low): 0 V
• 01 (128 Hz high): +Vdd
• 10 (64 Hz high): −Vdd
• 11 (both high): 0 V

The average is still 0, so the LCD won't be damaged, but as the voltage is zero for half the time, this could be compared to driving an LED with a 50% PWM signal. Fortunately, the opaqueness of the LCD isn't linear with the voltage, and once fully turned on, it can't get any darker. As a result, the colon is still as dark as the segments with fresh batteries, and can even act as a low battery indicator when it becomes fainter than the segments.

The segments are driven by one 4543 IC per digit. The ICs combine two functions: decoding the 4-bit BCD input to signals for the 7 display segments, and inverting the backplane signal for segments which should be visible. Inactive segments receive the same signal as the backplane, so the voltage between the two electrodes is always zero. The backplane waveform is provided to each IC at the PH (phase) input. The ICs also have two functions which are unused in the clock: BI (blanking input) is used to turn off all segments when driven high, and LE (latch enable) can be used to store the digit internally and not react to changes on the BCD inputs while driven low.